1. Field of the Invention
This invention relates to an integrated circuit chip, more particularly to an integrated circuit chip which can be manufactured at a lower cost within a shorter production time.
2. Description of the Related Art
FIG. 1 shows a die 20 which is adapted to be mounted on a lead frame (not shown) and which has a plurality of solder pads 40 formed at two sides of an upper surface thereof. At the central portion of the upper surface of the die 20, a circuit area 10 is provided. The pads 40 are connected electrically to circuit tracks (not shown) in the circuit area 10. Having fixed the die 20 on the lead frame, conventional wire bonding techniques are employed to connect electrically the solders pads 40 on the die 20 to the leads (not shown) of the lead frame. Referring now to FIG. 2, each of the aluminum wires 30 extends upward from the pads 40 and then downward to the leads so that the first end of each wire 30 can be connected electrically to a corresponding solder pad 40 while the second end of the same can be connected electrically to a corresponding lead. A layer of protective PV film (not shown) is then applied on the upper surface of the die 20. Lastly, the die 20 and the lead frame are packaged in a plastic package to form an integrated circuit chip. Note that damage to the film layer can occur because of the high temperature present during the packaging operation.
Referring now to FIG. 3, another type of die (20A) has a plurality of solder pads 50 formed at a central portion of an upper surface thereof. At two sides of the central portion of the upper surface of the die (20A), circuit areas 10 are provided. The pads 50 are connected electrically to circuit tracks (not shown) in the circuit areas 10. The die (20A) shown in FIG. 3 is also adapted to be mounted on a lead frame (not shown) and similarly undergoes conventional wire bonding techniques. However, referring to FIG. 4, since the distance between one pad 50 and the corresponding edges of the die (20A) is larger when compared to that of the die 20 in FIG. 2, and since the film layer is easily damaged during the packaging operation, the wires 30 may come into contact with the die (20A), thereby resulting in a short circuit condition. Furthermore, the inclusion of the packaging operation increases the production time, the manufacturing cost and the size of the integrated circuit chip.